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19-3148; Rev 4; 12/04
KIT ATION EVALU E AILABL AV
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
General Description Features
Guaranteed Monotonic to 16 Bits 32 Individual DACs in an 8mm x 8mm, 56-Pin, Thin QFN Package Four Output Voltage Ranges 0 to +5V 0 to +10V -2.5V to +7.5V -5V to +5V Buffered Voltage Outputs Capable of Driving 10k || 100pF Glitch-Free Power-Up SPI-/QSPI-/MICROWIRE-/DSP-Compatible 33MHz Serial Interface
MAX5732-MAX5735
The MAX5732-MAX5735 are 32-channel, 16-bit, voltageoutput, digital-to-analog converters (DACs). All devices accept a 3V external reference input. The devices include an internal offset DAC that allows all the outputs to be offset and a ground-sensing function, allowing output voltages to be referenced to a remote ground. A 33MHz SPITM-/QSPITM-/MICROWIRETM- and digital signal processor (DSP)-compatible serial interface controls the MAX5732-MAX5735. Each DAC has a doublebuffered input structure that helps minimize the digital noise feedthrough from the digital inputs to the outputs, and allows for synchronous or asynchronous updating of the outputs. The MAX5732-MAX5735 also provide a DOUT that allows for read-back or daisy chaining multiple devices. The devices provide separate power inputs for the analog and digital sections and provide separate power inputs for the output buffer amplifiers. The MAX5732-MAX5735 include proprietary deglitch circuits to prevent output glitches at power-up and eliminate the need for power sequencing. The devices provide a software-shutdown mode to allow efficient power management. The MAX5732-MAX5735 consume 50A of supply current in shutdown. The MAX5732-MAX5735 provide buffered outputs that can drive 10k in parallel with 100pF. The MAX5732 has a 0 to +5V output range; the MAX5733 has a 0 to +10V range; the MAX5734 has a -2.5V to +7.5V range; the MAX5735 has a -5V to +5V range. The MAX5732- MAX5735 are available in a 56-pin, 8mm x 8mm, thin QFN package in both the commercial (0C to +70C) and extended (-40C to +85C) temperature ranges.
Ordering Information
PART MAX5732ACTN* MAX5732BCTN MAX5732CCTN MAX5732AETN* MAX5732BETN MAX5732CETN MAX5733ACTN* MAX5733BCTN MAX5733CCTN MAX5733AETN* MAX5733BETN MAX5733CETN MAX5734ACTN* MAX5734BCTN MAX5734CCTN MAX5734AETN* MAX5734BETN MAX5734CETN MAX5735ACTN* MAX5735BCTN MAX5735CCTN MAX5735AETN* TEMP RANGE 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP** 56 Thin QFN-EP**
Applications
Automatic Test Systems Optical Router Controls Industrial Process Controls Arbitrary Function Generators Avionics Equipment Digital Offset/Gain Adjustment
SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Pin Configuration and Selector Guide appear at end of data sheet.
MAX5735BETN MAX5735CETN
*Future product--contact factory for availability. Specifications are preliminary. **EP = Exposed paddle (internally connected to VSS). 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
ABSOLUTE MAXIMUM RATINGS
AVCC to VSS, AGND, DGND, REFGND ..................-0.3V to +12V VSS to AGND, DGND................................................-6V to +0.3V AVDD, DVDD to AGND, DGND, REFGND.................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V REF to AGND, DGND, REFGND...............-0.3V to the lower of (AVDD + 0.3V) and +6V REFGND to AGND.................................................-0.3V to +0.3V Digital Inputs to AGND, DGND, REFGND..............-0.3V to the lower of (DVDD + 0.3V) and +6V DOUT to DGND.......-0.3V to the lower of (DVDD + 0.3V) and +6V OUT_ to VSS .........-0.3V to the lower of (AVCC + 0.3V) and +12V GS to AGND ................................................................-1V to +1V Maximum Current into REF...............................................10mA Maximum Current into Any Pin .........................................50mA Continuous Power Dissipation (TA = +70C) Thin QFN (derate 31.3mW/C above +70C)...................2.5W Operating Temperature Ranges MAX573__CTN....................................................0C to +70C MAX573__ETN .................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--MAX5732 (0 to +5V Output Voltage Range)
(AVCC = +5.25V to +5.5V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.0V, RL = , CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC CHARACTERISTICS Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient DC Crosstalk DYNAMIC CHARACTERISTICS Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough Digital Crosstalk Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Output Noise Spectral Density at 1kHz ANALOG OUTPUTS (OUT0 to OUT31) Output Voltage Range Resistive Load to Ground VSS = -0.5V, AVCC = +5V 0 10 50 5 V k (Note 6) (Note 7) Major carry transition (Note 8) Full-scale code Full-scale change to 0.5 LSB 20 1 5 5 120 15 250 s V/s nV-s nV-s nV-s nV-s nV/Hz VSS = -0.5V, AVCC = +5V (Note 5) N INL DNL VOS MAX5732B MAX5732C Guaranteed monotonic (Note 3) VSS = -0.5V, AVCC = +5.25V (Note 4) (Note 4) 8 8 0.1 20 50 16 8 32 16 64 1 40 50 0.5 40 250 Bits LSB LSB mV mV %FSR ppm FSR/C V SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5732 (0 to +5V Output Voltage Range) (continued)
(AVCC = +5.25V to +5.5V (Note 1), AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.0V, RL = , CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Capacitive Load to Ground DC Output Impedance Sourcing, full-scale code, output connected to AGND Short-Circuit Current Sinking, zero-scale code, output connected to AVCC GROUND-SENSE ANALOG INPUT (GS) Input Voltage Range GS Gain Input Resistance REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range 1 VREF Referred to REFGND 2.900 0.7 x DVDD 2.4 0.8 10 Digital inputs = 0 or DVDD 1 V pF A 3.000 3.100 M V VGS AGS -0.5V VGS +0.5V, VSS = -0.5V Relative to AGND -0.5 0.995 35 1.000 +0.5 1.005 V V/V k -5 SYMBOL CONDITIONS MIN TYP 50 0.1 5 mA MAX 100 UNITS pF
MAX5732-MAX5735
DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP) Input-Voltage High Input-Voltage Low Input Capacitance Input Current Output-Amplifier Positive Supply Voltage Output-Amplifier Negative Supply Voltage Output-Amplifier Supply Voltage Difference Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Output-Amplifier Positive Supply Current Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio AVDD DVDD AIDD DIDD AICC ISS PSRR VOUT0 through VOUT31 = 0 Software shutdown VIH = DVDD, VIL = 0, fSCLK = 20MHz VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz VOUT0 through VOUT31 = 0 Software shutdown VSS = -0.5V VOUT0 through VOUT31 = 0 Software shutdown VIH VIL CIN IIN DVDD = +2.7V to +3.6V DVDD = +4.75V to +5.25V V
POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) AVCC VSS AVCC - VSS 4.75 2.70 10 10 2.5 5 4 20 -4 -20 -95 -10 3.5 6.5 10 4.75 -0.5 5.50 0 5.75 5.25 5.25 15 V V V V V mA A mA mA A mA A dB
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3
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
ELECTRICAL CHARACTERISTICS--MAX5733 (0 to +10V Output Voltage Range)
(AVCC = +10.5V to +11V, AVDD = 5V 5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.0V, RL = , CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC CHARACTERISTICS Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient DC Crosstalk DYNAMIC CHARACTERISTICS Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough Digital Crosstalk Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Output Noise Spectral Density at 1kHz ANALOG OUTPUTS (OUT0 to OUT31) Output Voltage Range Resistive Load to Ground Capacitive Load to Ground DC Output Impedance Sourcing, full scale, output connected to AGND Short-Circuit Current Sinking, zero scale, output connected to AVCC GROUND-SENSE ANALOG INPUT (GS) Input Voltage Range GS Gain Input Resistance REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range 1 VREF Referred to REFGND 2.900 3.000 3.100 M V VGS AGS -0.5V VGS +0.5V, VSS = -0.5V Relative to AGND -0.5 0.995 70 1.000 +0.5 1.005 V V/V k -5 VSS = -0.5V, AVCC = +10.5V 0 10 50 50 0.1 5 mA 100 10 V k pF (Note 6) (Note 7) Major carry transition (Note 8) Full-scale code Full-scale change to 0.5 LSB 20 1 5 5 120 15 250 s V/s nV-s nV-s nV-s nV-s nV/Hz VSS = -0.5V, AVCC = +10V (Note 5) N INL DNL VOS MAX5733B MAX5733C Guaranteed monotonic (Note 3) VSS = -0.5V, AVCC = +10V (Note 4) (Note 4) 8 8 0.1 20 50 250 16 8 32 16 64 1 40 50 0.5 Bits LSB LSB mV mV % FSR ppm FSR/C V SYMBOL CONDITIONS MIN TYP MAX UNITS
4
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32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5733 (0 to +10V Output Voltage Range) (continued)
(AVCC = +10.5V to +11V, AVDD = 5V 5%, DVDD = +2.7V to AVDD, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.0V, RL = , CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN 0.7 x DVDD 2.4 0.8 10 Digital inputs = 0 or DVDD 1 V pF A TYP MAX UNITS DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP) Input-Voltage High Input-Voltage Low Input Capacitance Input Current VIH VIL CIN IIN DVDD = +2.7V to +3.6V DVDD = +4.75V to +5.25V V
MAX5732-MAX5735
POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) Output-Amplifier Positive Supply Voltage Output-Amplifier Negative Supply Voltage Output-Amplifier Supply Voltage Difference Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Output-Amplifier Positive Supply Current Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio AVDD DVDD AIDD DIDD AICC ISS PSRR VOUT0 through VOUT31 = 0 Software shutdown VIH = DVDD, VIL = 0, fSCLK = 20MHz VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz VOUT0 through VOUT31 = 0 Software shutdown VSS = -0.5V VOUT0 through VOUT31 = 0 Software shutdown AVCC VSS AVCC - VSS 4.75 2.70 10 10 2.5 5 4 20 -4 -20 -95 -10 3.5 6.5 10 10 -0.5 11 0 11 5.25 5.25 15 V V V V V mA A mA mA A mA A dB
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5
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
ELECTRICAL CHARACTERISTICS--MAX5734 (-2.5V to +7.5V Output Voltage Range)
(AVCC = +7.75V to +8.25V, AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -2.75V to -3.25V, AGND = DGND = REFGND = GS = 0, program the offset DAC to 4000hex. VREF = +3.0V, RL = , CL= 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC CHARACTERISTICS Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient DC Crosstalk DYNAMIC CHARACTERISTICS Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough Digital Crosstalk Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Output Noise Spectral Density at 1kHz ANALOG OUTPUTS (OUT0 to OUT31) Output Voltage Range Resistive Load to Ground Capacitive Load to Ground DC Output Impedance Sourcing, full scale, output connected to AGND Short-Circuit Current Sinking, zero scale, output connected to AVCC GROUND-SENSE ANALOG INPUT (GS) Input Voltage Range GS Gain Input Resistance REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range 1 VREF Referred to REFGND 2.900 3.000 3.100 M V VGS AGS -0.5V VGS +0.5V, VSS = -0.5V Relative to AGND -0.5 0.995 70 1.000 +0.5 1.005 V V/V k -5 VSS = -2.75V, AVCC = +7.75V -2.5 10 50 50 0.1 5 mA 100 +7.5 V k pF (Note 6) (Note 7) Major carry transition (Note 8) Full-scale code Full-scale change to 0.5 LSB 20 1 5 5 120 15 250 s V/s nV-s nV-s nV-s nV-s nV/Hz VSS = -3.25V, AVCC = +7.75V (Note 4) N INL DNL VOS MAX5734B MAX5734C Guaranteed monotonic (Note 3) VSS = -3.25V, AVCC = +7.75V (Note 4) (Note 4) 8 8 0.1 20 50 250 16 8 32 16 64 1 40 50 0.5 Bits LSB LSB mV mV %FSR ppm FSR/C V SYMBOL CONDITIONS MIN TYP MAX UNITS
6
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32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5734 (-2.5V to +7.5V Output Voltage Range) (continued)
(AVCC = +7.75V to +8.25V, AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -2.75V to -3.25V, AGND = DGND = REFGND = GS = 0, program the offset DAC to 4000hex. VREF = +3.0V, RL = , CL= 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN 0.7 x DVDD 2.4 0.8 10 Digital inputs = 0 or DVDD 1 V pF A TYP MAX UNITS DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP) Input-Voltage High Input-Voltage Low Input Capacitance Input Current Output-Amplifier Positive Supply Voltage Output-Amplifier Negative Supply Voltage Output-Amplifier Supply Voltage Difference Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Output-Amplifier Positive Supply Current Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio AVDD DVDD AIDD DIDD AICC ISS PSRR VOUT0 through VOUT31 = 0 Software shutdown VIH = DVDD, VIL = 0, fSCLK = 20MHz VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz VOUT0 through VOUT31 = 0 Software shutdown VSS = -2.75V VOUT0 through VOUT31 = 0 Software shutdown VIH VIL CIN IIN DVDD = +2.7V to +3.6V DVDD = +4.75V to +5.25V V
MAX5732-MAX5735
POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) AVCC VSS AVCC - VSS 4.75 2.70 10 10 2.5 5 4 20 -4 -20 -95 -10 3.5 6.5 10 7.50 -3.25 8.25 -2.50 11 5.25 5.25 15 V V V V V mA A mA mA A mA A dB
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7
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
ELECTRICAL CHARACTERISTICS--MAX5735 (-5V to +5V Output Voltage Range)
(AVCC = +5.25V to +5.5V, AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -5.25V to -5.5V, AGND = DGND = REFGND = GS = 0, program the offset DAC to 8000hex. VREF = +3.0V, RL = , CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER DC CHARACTERISTICS Resolution Integral Nonlinearity (Note 2) Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient DC Crosstalk DYNAMIC CHARACTERISTICS Output-Voltage Settling Time Voltage-Output Slew Rate Digital Feedthrough Digital Crosstalk Digital-to-Analog Glitch Impulse (Note 6) (Note 7) Major carry transition Full-scale change to 0.5 LSB 20 1 5 5 120 15 250 s V/s nV-s nV-s nV-s nV-s nV/Hz VSS = -5.75V, AVCC = +5.25V (Note 5) N INL DNL VOS MAX5735B MAX5735C Guaranteed monotonic (Note 3) VSS = -5.25V, AVCC = +5.25V (Note 4) (Note 4) 8 8 0.1 20 50 250 16 8 32 16 64 1 40 50 0.5 Bits LSB LSB mV mV %FSR ppm FSR/C V SYMBOL CONDITIONS MIN TYP MAX UNITS
DAC-to-DAC Crosstalk (Note 8) Output Noise Spectral Density at Full-scale code 1kHz ANALOG OUTPUTS (OUT0 through OUT31) Output Voltage Range Resistive Load to Ground Capacitive Load to Ground DC Output Impedance Sourcing, full scale, output connected to AGND Short-Circuit Current Sinking, zero scale, output connected to AVCC GROUND-SENSE ANALOG INPUT (GS) Input Voltage Range GS Gain Input Resistance REFERENCE INPUT (REF) Input Resistance Reference Input Voltage Range VREF Referred to REFGND 1 2.900 VGS AGS -0.5V VGS +0.5V, VSS = -0.5V Relative to AGND -0.5 0.995 70 VSS = -5.25V, AVCC = +5.25V -5 10
+5 50 50 0.1 5 100
V k pF
mA -5
+0.5 1.000 1.005
V V/V k M
3.000
3.100
V
8
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32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS--MAX5735 (-5V to +5V Output Voltage Range) (continued)
(AVCC = +5.25V to +5.5V, AVDD = +5V 5%, DVDD = +2.7V to AVDD, VSS = -5.25V to -5.5V, AGND = DGND = REFGND = GS = 0, program the offset DAC to 8000hex. VREF = +3.0V, RL = , CL = 50pF referenced to ground, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS MIN 0.7 x DVDD 2.4 0.8 10 Digital inputs = 0 or DVDD 1 V pF A TYP MAX UNITS DIGITAL INPUTS (CS, SCLK, DIN, LDAC, CLR, DSP) Input-Voltage High Input-Voltage Low Input Capacitance Input Current Output-Amplifier Positive Supply Voltage Output-Amplifier Negative Supply Voltage Output-Amplifier Supply Voltage Difference Analog Supply Voltage Digital Supply Voltage Analog Supply Current Digital Supply Current Output-Amplifier Positive Supply Current Output-Amplifier Negative Supply Current Power-Supply Rejection Ratio AVDD DVDD AIDD DIDD AICC ISS PSRR VOUT0 through VOUT31 = 0 Software shutdown VIH = DVDD, VIL = 0, fSCLK = 20MHz VIH = +2.4V, VIL = +0.8V, fSCLK = 20MHz VOUT0 through VOUT31 = 0 Software shutdown VSS = -0.5V VOUT0 through VOUT31 = 0 Software shutdown VIH VIL CIN IIN DVDD = +2.7V to +3.6V DVDD = +4.75V to 5.25V V
MAX5732-MAX5735
POWER REQUIREMENTS (AVCC, VSS, AGND, AVDD, DVDD, DGND) AVCC VSS AVCC - VSS 4.75 2.70 10 10 2.5 5 4 20 -4 -20 -95 -10 3.5 6.5 10 4.75 -5.50 5.50 -4.75 11 5.25 5.25 15 V V V V V mA A mA mA A mA A dB
Note 1: AVCC should be at least 0.25V higher than the maximum output voltage required from the DAC. Full-scale output is 5V for the MAX5732. Note 2: Linearity guaranteed from code 2047 to full scale and from (VSS + 0.3V) to (AVCC - 0.3V). Note 3: DNL guaranteed over all codes for (VSS + 0.3V) to (AVCC - 0.3V). Note 4: Zero-scale error is measured at code 0. Full-scale error is measured at code FFFFhex. Note 5: DC crosstalk is the change in the output level of one DAC at midscale in response to the full-scale output change of all other DACs. Note 6: Digital feedthrough is a measure of the impulse injected into the analog outputs from the digital control inputs when the device is not being written to. It is measured with a worst-case change on the digital inputs. Note 7: Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale while a full-scale code change is written into another DAC. Note 8: DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one converter due to both the digital change and subsequent analog output change at another converter.
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9
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
TIMING CHARACTERISTICS--DVDD = +4.75V to +5.25V
(Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +4.75V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Serial Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Fall to CS Fall Setup Time CS Fall to SCLK Fall Setup Time CS Rise to SCLK Fall SCLK Fall to CS Rise Setup Time DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Fall to DOUT Fall SCLK Fall to DOUT Rise CS Pulse-Width High CS Pulse-Width Low LDAC Pulse-Width Low CLR Pulse-Width Low SYMBOL fSCLK tCH tCL tSCS tCSS tCS1 tCS2 tDS tDH tSCL tSDH tCSPWH tCSPWL tLDAC tCLR Load capacitance = 20pF Load capacitance = 20pF 50 20 20 20 At end of cycle in SPI mode only CONDITIONS MIN 0 10 10 6 5 15 0 10 2 20 20 TYP MAX 33 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
TIMING CHARACTERISTICS--DVDD = +2.7V to +5.25V
(Figures 2 and 3, AVDD = +4.75V to +5.25V, DVDD = +2.7V to +5.25V, AGND = DGND = REFGND = GS = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Serial Clock Frequency SCLK Pulse-Width High SCLK Pulse-Width Low SCLK Fall to CS Fall Setup Time CS Fall to SCLK Fall Setup Time CS Rise to SCLK Fall SCLK Fall to CS Rise Setup Time DIN to SCLK Fall Setup Time DIN to SCLK Fall Hold Time SCLK Fall to DOUT Fall SCLK Fall to DOUT Rise CS Pulse-Width High CS Pulse-Width Low LDAC Pulse-Width Low CLR Pulse-Width Low SYMBOL fSCLK tCH tCL tSCS tCSS tCS1 tCS2 tDS tDH tSCL tSDH tCSPWH tCSPWL tLDAC tCLR Load capacitance = 20pF Load capacitance = 20pF 50 20 20 20 At end of cycle in SPI mode only CONDITIONS MIN 0 10 10 10 10 18 0 10 2 25 25 TYP MAX 25 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
10
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32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
Typical Operating Characteristics
(AVCC = +10.5V 5%, AVDD = +5V 5%, DVDD = +5V, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.000V, RL = , CL = 50pF referenced to ground, output gain = 2.5, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C).
INTEGRAL NONLINEARITY vs. INPUT CODE
MAX5732 toc01
MAX5732-MAX5735
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
MAX5732 toc02
WORST-CASE INL vs. TEMPERATURE
MAX5732 toc03
5 4 3
0.4 0.3 0.2 DNL (LSB)
3.0 2.5 2.0 INL (LSB) 1.5 1.0 0.5 0
INL (LSB)
2 1 0 -1 0 10k 20k 30k 40k 50k 60k 70k INPUT CODE
0.1 0 -0.1 -0.2 0 10k 20k 30k 40k 50k 60k 70k INPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (C)
WORST-CASE DNL vs. TEMPERATURE
MAX5732 toc04
ZERO-SCALE ERROR vs. TEMPERATURE
MAX5732 toc05
FULL-SCALE ERROR vs. TEMPERATURE
4.5 FULL-SCALE ERROR (mV) 4.0 3.5 3.0 2.5 2.0 1.5 1.0
MAX5732 toc06
0.25
6 5 ZERO-SCALE ERROR (mV) 4 3 2 1 VSS = -0.5V 0
5.0
0.20
DNL (LSB)
0.15 0.10
0.05
0.5 0 85 -40 -15 10 35 60 85
0 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
TEMPERATURE (C)
TEMPERATURE (C)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX5732 toc07
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX5732 toc08
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
110 109 108 DVDD (A) 107 106 105 104 103
MAX5732 toc09
9.0 8.9 8.8 8.7 AVDD (mA)
60 59 58 57 DVDD (A) 56 55 54 53 52 51 50 ALL DIGITAL INPUTS AT ZERO OR DVDD -40 -15 10 35 DVDD = +3V 60
111
8.6 8.5 8.4 8.3 8.2 8.1 8.0 -40 -15 10 35 60 85 TEMPERATURE (C)
102 101 85
ALL DIGITAL INPUTS AT ZERO OR DVDD -40 -15 10 35
DVDD = +5V 60 85
TEMPERATURE (C)
TEMPERATURE (C)
______________________________________________________________________________________
11
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
Typical Operating Characteristics (continued)
(AVCC = +10.5V 5%, AVDD = +5V 5%, DVDD = +5V, VSS = AGND = DGND = REFGND = GS = 0, VREF = +3.000V, RL = , CL = 50pF referenced to ground, output gain = 2.5, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C).
LARGE-SIGNAL STEP RESPONSE (LOW TO HIGH)
MAX5732 toc11
DIGITAL FEEDTHROUGH
MAX5732 toc10
LARGE-SIGNAL STEP RESPONSE (HIGH TO LOW)
MAX5732 toc12
CS 5V/div SCLK 5V/div
CS 5V/div
OUT_ 10mV/div
OUT_ 5V/div
OUT_ 5V/div
400ns/div
2s/div
2s/div
NOISE VOLTAGE DENSITY
1000
MAX5732 toc13
MAJOR CARRY TRANSITION (7FFFhex TO 8000hex)
MAX5732 toc14
MAJOR CARRY TRANSITION (8000hex TO 7FFFhex)
MAX5732 toc15
NOISE (nV/Hz)
100
CS 5V/div
CS 5V/div
10 OUT_ 20mV/div OUT_ 20mV/div
1 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) 1s/div 1s/div
12
______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
Pin Description
PIN 1, 42, 48 2 3 4 5 6 7 8 9, 38 10 11, 28, 39 12 13 14 15 16 17 18 19 20 21 22 23 24 25, 49 26 27, 50 29 30 31 32 33 34 35 36 37 NAME AVCC OUT9 OUT8 OUT7 N.C. OUT6 OUT5 OUT4 AGND OUT3 VSS OUT2 OUT1 OUT0 DSP CS DOUT SCLK DIN DVDD DGND LDAC CLR GS REFGND REF AVDD OUT31 OUT30 OUT29 OUT28 OUT27 OUT26 OUT25 OUT24 OUT23 DAC9 Buffered Analog Output Voltage DAC8 Buffered Analog Output Voltage DAC7 Buffered Analog Output Voltage No Connection. Internally connected. Do not make any connections to N.C. DAC6 Buffered Analog Output Voltage DAC5 Buffered Analog Output Voltage DAC4 Buffered Analog Output Voltage Analog Ground DAC3 Buffered Analog Output Voltage Output-Amplifier Negative Supply Input DAC2 Buffered Analog Output Voltage DAC1 Buffered Analog Output Voltage DAC0 Buffered Analog Output Voltage Digital Serial-Interface-Select Input. Drive low for DSP-interface mode. Drive high for SPI-interface mode. Active-Low Digital Chip-Select Input Digital Serial-Data Output. Use DOUT to daisy chain and read the contents of the DAC registers. Digital Serial-Clock Input Digital Serial-Data Input Digital Power-Supply Input. Bypass to DGND with a 0.1F capacitor. Digital Ground Active-Low Digital Load DAC Input. Drive this asynchronous input low to transfer the contents of the input register to their respective DAC registers and set all DAC outputs accordingly. Active-Low Digital Clear Input. Drive this asynchronous input low to clear the contents of the input and DAC registers and set all the DAC outputs to zero. Ground-Sense Analog Input. Offsets the DAC amplifier outputs by 0.5V to compensate for a remote system ground potential difference. Reference Ground Analog Reference Voltage Input Analog Power-Supply Input. Bypass to AGND with a 0.1F capacitor. DAC31 Buffered Analog Output Voltage DAC30 Buffered Analog Output Voltage DAC29 Buffered Analog Output Voltage DAC28 Buffered Analog Output Voltage DAC27 Buffered Analog Output Voltage DAC26 Buffered Analog Output Voltage DAC25 Buffered Analog Output Voltage DAC24 Buffered Analog Output Voltage DAC23 Buffered Analog Output Voltage FUNCTION Output-Amplifier Positive Supply Input. Bypass to VSS with a 0.1F capacitor.
MAX5732-MAX5735
______________________________________________________________________________________
13
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
Pin Description (continued)
PIN 40 41 43 44 45 46 47 51 52 53 54 55 56 -- NAME OUT22 OUT21 OUT20 OUT19 OUT18 OUT17 OUT16 OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 EP DAC22 Buffered Analog Output Voltage DAC21 Buffered Analog Output Voltage DAC20 Buffered Analog Output Voltage DAC19 Buffered Analog Output Voltage DAC18 Buffered Analog Output Voltage DAC17 Buffered Analog Output Voltage DAC16 Buffered Analog Output Voltage DAC15 Buffered Analog Output Voltage DAC14 Buffered Analog Output Voltage DAC13 Buffered Analog Output Voltage DAC12 Buffered Analog Output Voltage DAC11 Buffered Analog Output Voltage DAC10 Buffered Analog Output Voltage Exposed Paddle. Internally connected to VSS. Connect externally to a metal pad for improved thermal dissipation. FUNCTION
14
______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
AVCC INPUT REGISTER DAC0 REGISTER DAC0 OUT0
VSS
AVCC INPUT REGISTER DAC1 REGISTER DAC1 OUT1
VSS
AVCC INPUT REGISTER DAC_ REGISTER DAC_ OUT_
VSS
AVCC INPUT REGISTER DAC30 REGISTER DAC30 OUT30
VSS
AVCC INPUT REGISTER DAC31 REGISTER DAC31 OUT31
VSS
INPUT REGISTER
OFFSET DAC REGISTER
AVCC OFFSET DAC VSS AGND POWER MANAGEMENT AVDD DVDD
DIGITAL CONTROL LOGIC
DOUT
LDAC
SCLK
DSP
CLR
DIN
CS
REF
Figure 1. Functional Diagram
______________________________________________________________________________________
GS
MAX5732 MAX5733 MAX5734 MAX5735
DGND REFGND
15
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
Detailed Description
The MAX5732-MAX5735 are 32-channel, 16-bit, voltage-output DACs (Figure 1). The devices accept a 3V external reference input at REF. An internal offset DAC allows all outputs to be offset (see Table 1). The devices provide a ground-sensing function that allows the output voltages to be referenced to a remote ground. A 33MHz SPI-/QSPI/-MICROWIRE- and DSP-compatible serial interface controls the MAX5732-MAX5735 (Figure 2). Each DAC includes a double-buffered input structure to minimize the digital noise feedthrough from the digital inputs to the outputs, and allows for synchronous or asynchronous updating of the outputs. The two buffers are organized as an input register followed by a DAC register that stores the contents of the output. Input registers update the DAC registers independently or simultaneously with a single software or hardware command. The MAX5732-MAX5735 also have a DOUT that allows for read-back or daisy chaining multiple devices. The MAX5732-MAX5735 analog and digital sections have separate power inputs. Separate power inputs are also provided for the output buffer amplifiers. Proprietary deglitch circuits prevent output glitches at power-up and eliminate the need for power sequencing. A software-shutdown mode allows efficient power management. The MAX5732-MAX5735 consume 50A of supply current in shutdown. All DACs provide buffered outputs that can drive 10k in parallel with 100pF. The MAX5732 has a 0 to +5V output range; the MAX5733 has a 0 to +10V output range; the MAX5734 has a -2.5V to +7.5V output range; and the MAX5735 has a -5V to +5V output range. The MAX5732-MAX5735 are available in a 56-pin 8mm x 8mm thin QFN package and are specified over the extended -40C to +85C temperature range.
External Reference Input (REF)
The REF voltage sets the full-scale output voltage for all 32 DACs. REF accepts a +3V 3% input. Reference voltages outside these limits can result in a degradation of device performance. REF is a buffered input. The typical input impedance is 10M, and it does not vary with code. Use a highaccuracy, low-noise voltage reference such as the MAX6126AASA30 (3ppm/C temp drift and 0.02% initial accuracy) to improve static accuracy. REF does not accept AC signals.
Ground Sense (GS)
The MAX5732-MAX5735 include a GS that allows the output voltages to be referenced to a remote ground. The GS input voltage range (VGS) is -0.5V to +0.5V. VGS is added to the output voltage with unity gain. The resulting output voltage must be within the valid outputvoltage range set by the power supplies. See the Output Amplifiers (OUT0-OUT31) section for the effect of the GS inputs on the DAC outputs.
Offset DAC
The MAX5732-MAX5735 feature an offset DAC that determines the output voltage range. While each part number has an output voltage range associated with it,
tCL
tCH
SCLK
X
X
1 tDH
2
3
32
X
DIN tSCS
C2 tDS
C1
C0
D0 tCS1 tCS2
CS (C MODE) tCSPWH CS (DSP MODE)
tCSS
tCSPWL
Figure 2. Serial-interface Timing 16 ______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
Table 1. Offset DAC Codes
PART NUMBER MAX5732 MAX5733 MAX5734 MAX5735 D15 0 0 0 1 D14 0 0 1 0 D13 0 0 0 0 D12 0 0 0 0 D11 0 0 0 0 D10 0 0 0 0 D9 0 0 0 0 D8 0 0 0 0 D7 0 0 0 0 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 0 0 D3 0 0 0 0 D2 0 0 0 0 D1 0 0 0 0 D0 0 0 0 0
Note: For the MAX5732, the maximum code for the offset DAC is 16384. For the MAX5733/MAX5734/MAX5735, the maximum code for the offset DAC is 40000.
it is the offset DAC that determines the end-point voltages of the range. Table 1 shows the offset DAC code required during power-up. Note: The offset DAC of every device can be programmed with any of the four output voltage ranges. However, the specifications in the Electrical Characteristics table are only guaranteed (production tested) for the offset code associated with each particular part number. For example, the MAX5734 specifications are only valid with the MAX5734 offset- DAC code shown in Table 1. The offset DAC is summed with GS (Figure 1). The offset DAC can also cancel the offset of the output buffers. Any change in the offset DAC affects all 32 DACs. The offset DAC is also configured identically to the other 32 DACs with an input and DAC register. Write to the offset DAC through the serial interface by using control bits C2, C1, and C0 = 001 followed by the data bits D15-D0. The CLR command affects the offset DAC as well as the other DACs. The data format for the offset DAC codes are: control bits C2, C1, and C0 = 011, address bits A5-A0 = 100000, 7 don't-care bits, and 16 data bits as shown in Table 2. Output Amplifiers (OUT0-OUT31) All DAC outputs are internally buffered. The internal buffers provide gain, improved load regulation, and transition glitch suppression for the DAC outputs. The output buffers slew at 1V/s and can drive 10k in parallel with 100pF. The output buffers are powered by AVCC and
Table 2. Serial Data Format
CONTROL BITS C2, C1, AND C0 011 ADDRESS BITS A5-A0 100000 DON'TCARE BITS -- XXXXXXX DATA BITS
D15-D0 See table 1
VSS. AVCC and VSS determine the maximum output voltage range of the device. The input code, the voltage reference, the offset DAC output, the voltage on GS, and the gain of the output amplifier determine the output voltage. Calculate VOUT as follows:
VOUT = GAIN x VREF x (DAC code - offset DAC code) 216 + VGS
where GAIN = 5/3 for the MAX5732, or GAIN = 10/3 for the MAX5733/MAX5734/MAX5735.
Load-DAC (LDAC) Input
The MAX5732-MAX5735 feature an active-low LDAC logic input that allows the outputs OUT_ to update asynchronously. Keep LDAC high during normal operation (when the device is controlled only through the serial interface). Drive LDAC low to simultaneously update all DAC outputs with data from their respective input registers. Figure 3 shows the LDAC timing with respect to OUT_.
LDAC
tLDAC
0.5 LSB tS
OUT_
Figure 3. LDAC Timing ______________________________________________________________________________________ 17
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
A software command can also activate the LDAC operation. To activate LDAC by software, set control bits C2, C1, and C0 = 010, address bits A5-A0 = 111111, and all data bits to don't care. See Table 3 for the data format. This operation updates all DAC outputs. Note: The software load DAC does not affect the offset DAC.
Serial Interface
A 3-wire SPI-/QSPI-/MICROWIRE- and DSP-compatible serial interface controls the MAX5732-MAX5735. The interface requires a 32-bit command word to control the device. The command word consists of 3 control bits, 6 address bits, 7 don't-care bits, and 16 data bits. Table 5 shows the general serial-data format. The control bits control various write and read commands as well as the load DAC and clear commands. Table 6 shows the control-bit functions. The address bits select the register(s) to be written. Table 7 shows the address functions. The data bits control the value of the DAC outputs.
Clear (CLR)
The MAX5732-MAX5735 feature an active-low CLR logic input that sets all channels including the offset DAC to 0V (code 0000hex). The offset DAC needs to be reprogrammed after CLR is asserted. Driving CLR low clears the contents of both the input and DAC registers. The serial interface can also issue a software clear command. Setting the control bits C2, C1, and C0 = 111 (Table 4) performs the same function as driving logicinput CLR low. Table 4 shows the clear-data format for the software-controlled clear command. This registerreset process cannot be interrupted. All serial input data is ignored until the entire reset process is complete.
Table 6. Control-Bit Functions
CONTROL BITS C2 C1 C0 CONTROL-BIT DESCRIPTION
Table 3. Load-DAC Data Format
0 CONTROL BITS C2, C1, AND C0 010 ADDRESS BITS A5-A0 111111 DON'TCARE BITS -- XXXXXXX DATA BITS 0 0
No operation (NOP); no internal registers change state. The NOP command can be passed to DOUT depending on the state of the configuration register. Address bits A5-A0 and data bits D15-D0 are ignored. Loads D15-D0 into the input register(s) for the selected address. Depending on the address bits, this command could write to: The configuration register (A[5:0] = 100001) One of the input registers of the 32 DAC channels All 32 DAC input registers (A[5:0] = 111111) The offset DAC input register (A[5:0] = 100000) Loads DAC register(s) from the input register(s). Depending on the address bits, this command can update one or all of the DAC registers from the stored input register value(s). Data bits D15-D0 are ignored. Write-through; loads D15-D0 into the input and DAC registers, depending on the address bits. Read command; depending on the address bits, one of the DAC-register values or the configuration-register value may be read back through DOUT. Data bits D15-D0 are ignored. Reserved for internal testing; do not use. Reserved for internal testing; do not use. Clear register(s); depending on the address bits, one or all registers (except the offset-DAC registers) are cleared to zero. Data bits D15-D0 are ignored.
D15-D0 XXXXXXXXXXXXXXXX 0 0 1
Table 4. Clear-Data Format
CONTROL BITS C2, C1, AND C0 111 ADDRESS BITS A5-A0 See table 7 DON'TCARE BITS -- XXXXXXX DATA BITS 0 1 0
D15-D0 XXXXXXXXXXXXXXXX 0 1 1
Table 5. Serial-Data Format
CONTROL BITS MSB C2, C1, and C0 A5-A0 XXXXXXX D15-D0 ADDRESS BITS DON'TCARE BITS DATA BITS LSB
1
0
0
1 1 1
0 1 1
1 0 1
18
______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
Table 7. Address-Bit Functions
ADDRESS BITS A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CONTROL FUNCTION DAC0 DAC1 DAC2 DAC3 DAC4 DAC5 DAC6 DAC7 DAC8 DAC9 DAC10 DAC11 DAC12 DAC13 DAC14 DAC15 DAC16 DAC17 DAC18 DAC19 DAC20 DAC21 DAC22 DAC23 DAC24 DAC25 DAC26 DAC27 DAC28 DAC29 DAC30 DAC31 Offset DAC Configuration register; control bits C2, C1, and C0 = 010 and C2, C1, and C0 = 011 set the error flag in the configuration register. Do not use these control bits with these address bits. 1 1 1 1 1 1 ADDRESS BITS A5 A4 A3 A2 A1 A0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 CONTROL FUNCTION Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. Command reserved; do not use. All channels (DAC31-DAC0); used for write commands only. Read commands cannot be used with these address bits.
1
0
0
0
0
1
______________________________________________________________________________________
19
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
Table 8. Configuration-Register Data Format
16 DATA BITS D15 ERRF D14 SING D13 GLT D12 DT D11 SHDN D10 X D9 X D8 X D7 X D6 X D5 X D4 X D3 X D2 X D1 X D0 X
X = Don't care.
Table 9. Configuration-Register Commands
DATA BIT NAME DESCRIPTION Error flag; ERRF goes logic-high when an invalid command is attempted. ERRF is cleared each time the configuration register is read back to DOUT. Clear-register commands C2, C1, and C0 = 111 resets ERRF. Conditions that trigger ERRF include: Attempted read of address bits A5-A0 = 111111 (all 32 DACs) Access to reserved addresses Access to the configuration register (address bits A5-A0 = 100001 when used with control bits C2, C1, and C0 = 010 and 011) Default is logic-low (no error flags); ERRF is read only. Single device; SING determines the manner in which data is output to DOUT. A logic-high sets the device to operate in stand-alone mode or in parallel; only the 16 data bits are output to DOUT. A logic-low sets the device to operate in a daisy chain of devices. In this case, the entire 32-bit command word is output to DOUT. Default is logic-low (daisy-chain mode); SING is read/write. Glitch-suppression enable; the MAX5732-MAX5735 feature glitch-suppression circuitry on the analog outputs that minimizes the output glitch during a major carry transition. A logic-low disables the internal glitch-suppression circuitry, which improves settling time. A logic-high enables glitchsuppression, suppressing up to 120nV-s glitch impulse on the DAC outputs. Default is logic-low (glitch suppression disabled); GLT is read/write. Digital output enable; a logic-low enables DOUT. A logic-high disables DOUT. Disabling DOUT reduces power consumption and digital noise feedthrough to the DAC outputs from the DOUT output buffer. Default is logic-low (DOUT enabled); DT is read/write. Shutdown; a logic-high shuts down all 32 DACs. The logic interface remains active, and the data is retained in the input and DAC registers. Read/write operations can be performed while the device is disabled; however, no changes can occur at the device outputs. A logic-low powers up all 32 DACs if the device was previously in shutdown. Upon waking up, the DAC outputs return to the last stored value in the DAC registers. Default is logic-low (normal operation); SHDN is read/write. Don't care.
D15
ERRF
D14
SING
D13
GLT
D12
DT
D11
SHDN
D10-D0
X
DSP Mode (DSP) The MAX5732-MAX5735 provide a hardware-selectable DSP-interface mode. DSP mode, when active, allows chip select (CS) to go high before the entire 32-bit command word is clocked in. The active-low DSP logic input selects microcontroller (C)- or DSP-interface mode. Drive DSP low for DSP-interface mode. Drive DSP high for C-interface mode. Figure 2 illustrates serial timing for both C- and DSP-interface modes.
20
Configuration Register The configuration register controls the advanced features of the MAX5732-MAX5735. Write to the configuration register by setting the control bits C2, C1, and C0 = 001 and address bits A5-A0 = 100001. Table 8 shows the configuration-register data format for the D15-D0 data bits. Table 9 shows the commands controlled by the configuration register.
______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
SING When SING = 0 (default power-up mode), the device is in daisy-chain mode. DOUT follows DIN after 32 clock cycles. For the read command, DOUT provides the read data in the next cycle following CS rising edge. The 16 data bits of the previous command word are clocked out on the last 16 clock cycles of the current command word. When SING = 1, the device is in stand-alone mode. To reduce the time it takes to read data out, the read data is provided at DOUT as the 16 data bits of the current command are clocked in. The device acts on an incoming command word independent of the rising edge of CS.
MAX5732-MAX5735
CONTROLLER DEVICE 1
MAX573_ DIN(0) SCLK DOUT(0) CS DSP
MAX573_ DIN(1) SCLK DOUT(1) CS DSP
Daisy Chain Operation
Any number of the MAX5732-MAX5735 devices can be daisy chained by connecting the DOUT of one device to the DIN of another device in a chain. All devices must be in SING = 0 mode. Connecting the CS inputs of all devices together eliminates the need to issue NOP commands to devices early in the chain (see Figure 4). Data Readback The contents of the MAX5732-MAX5735 DAC and configuration registers can be read on DOUT by issuing a read-data command. Setting control bits C2, C1, and C0 = 100, puts the device in read-data mode. The address bits select the register to be read. The contents of the register (16 data bits) are clocked out at DOUT. The output-data format depends on the status of DSP and SING. Table 10 shows the manner in which
MAX573_ DIN(2) SCLK DOUT(2) CS DSP
Figure 4. Daisy-Chain Configuration
data is written to DOUT. Note that when the device is in DSP mode (DSP = 0), only the 16-bit data of the selected register is written to DOUT.
Table 10. Read-Data Modes with SING and DSP Controls
DSP SING CONFIGURATION DESCRIPTION Stand alone READ DATA AT DOUT DOUT provides the 16 data bits from the previous command word. Data appears at DOUT on the last 16 clock edges of the current command word. See Figure 7. DOUT provides the 16 data bits from the current command word. Data appears at DOUT on the last 16 clock edges of the current command word. See Figure 7. Data on DOUT follows the current command word after 32 clock cycles. For read commands, the read data from the previous command word appears at DOUT on the last 16 clock edges of the current command word. See Figure 4.
0
0
0
1
Stand alone
1
0
Daisy chain
1
1
DOUT provides the 16 data bits from the current command word. Data appears Multiple DOUTs connected at DOUT on the last 16 clock edges of the current command word. For read in parallel (not daisy commands, the read data from the current command word appears at DOUT chained) on the last 16 clock edges of the current command word. See Figures 8 and 9.
______________________________________________________________________________________
21
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
DIN(0) W WD2 W WD1 W WD0 R XX R XX R XX X XX X XX X XX
CS
DOUT(0)
W WD2
W WD1
W
WD0
R
XX
R
XX
R RD0
X
XX
X
XX
DOUT(1)
W WD2
W
WD1 W
WD0
R
XX
R
RD1
R
RD0
X
XX
DOUT(2)
W WD2
W WD1
W WD0
R
RD2
R
RD1
R
RD0
Figure 5. Example 1 of a Daisy-Chain Data Sequence W/WD0 = 32-bit word with a write command; WD0 writes data for device 0. The 0 refers to the position in the daisy chain (0 is closest to the bus master). Devices 1 and 2 are devices further down the chain. R/RD2 = 32-bit word with a read command; RD2 reads data from device 2. X = Don't care (for X in the data or command position).
DIN(0)
W
WD2 R
XX
W WD0
R
XX
W
WD1
R
XX
X
XX
X
XX
X
XX
CS
DOUT(0)
W WD2
R
XX
W
WD0
R
XX
W
WD1
R
RD0
X
XX
X
XX
DOUT(1)
W WD2
R
RD1
W
WD0
R
XX
W
WD1
R
RD0
X
XX
DOUT(2)
W WD2
R
RD1
W WD0
R
RD2
W
WD1
R
RD0
Figure 6. Example 2 of a Daisy-Chain Data Sequence W/WD0 = 32-bit word with a write command; WD0 writes data for device 0. The 0 refers to the position in the daisy chain (0 is closest to the bus master). Devices 1 and 2 are devices further down the chain. R/RD2 = 32-bit word with a read command; RD2 reads data from device 2. X = Don't care (for X in the data or command position).
22
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32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
MAX573_ DIN SCLK DOUT CS 1 OR 0 DSP
CONTROLLER DEVICE
Read-Data Format The MAX5732-MAX5735 support daisy-chain connections of multiple devices. The default (power-up) configuration for the MAX5732-MAX5735 assumes that the device may be part of a daisy chain of devices. DOUT follows DIN after 32 clock cycles. For a read command, DOUT provides read data (instead of the data value shifted in) in the next cycle following a CS rising edge. Figures 5 and 6 show examples of daisy-chain data sequences.
MAX5732-MAX5735
Figure 7. Stand-Alone Configuration
Shutdown Mode
The MAX5732-MAX5735 feature a software-controlled low-power shutdown mode. When bit 11 of the configuration register is a logic high, the analog section of the device is disabled, and the outputs go high impedance. In shutdown, supply current is reduced to 50A. Data stored in the DAC and input registers is retained, and the device outputs return to their previous values when the device is brought out of shutdown. The serial interface remains active while the device is in shutdown.
CONTROLLER DEVICE 1 OR 0
MAX573_ DIN SCLK DOUT CS DSP
MAX573_ DIN SCLK DOUT CS 1 OR 0 DSP
Power-Up State
The MAX5732-MAX5735 monitor the four power supplies and maintain the output buffers in a known state until sufficient voltage is available to ensure that no output glitches occur. Once the minimum voltage threshold has been passed, the device outputs come up in the clear state (all outputs = 0). For proper power sequencing, VSS must be applied first. Power sequencing is not necessary if VSS is connected to AGND.
MAX573_ DIN SCLK DOUT CS 1 OR 0 DSP
Figure 8. Example of a Parallel Configuration with Read-Back
DIN(0) C2 C1 C0 A5 A4 A3 A2 A1 A0 Sp Sp Sp Sp Sp Sp Sp D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SCLK CS (C) OR CS (DSP) DOUT(0) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 9. Read Data Timing When Not Daisy Chained ______________________________________________________________________________________ 23
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
HVDRV0 DAC0 VOLTAGE REFERENCE MAX5732 MAX5733 DAC31 HVDRV31
14 TO 16 BITS
CONTROL ALGORITHM
DSP
DWDM PIPE
MEMS MIRRORS WITH X AND Y CONTROL
14 TO 16 BITS ADC
POSITION OR OPTICAL FEEDBACK VOLTAGE REFERENCE PGA OR FIXED GAIN AMPS
THIN-FILM FILTER OR PLANAR LIGHT WAVE SEPARATORS WITH OPTICAL LENSES
MEMS MIRRORS WITH X AND Y CONTROL
DWDM PIPE
OPTICAL LENSES AND COLLIMATORS
Figure 10. MEMS Mirror Control
Applications Information
MEMS Micromirror Control
The MAX5732/MAX5733 are the highest resolution 32channel DACs available in the smallest footprint, making the devices ideal for optical MEMS mirror control (Figure 10). A high-resolution DAC forms the core analog block for controlling the X and Y position of the mirror. As the density of the optical cross-connects increases, the number of DAC channels also increases. By offering the highest resolution and the greatest density, the MAX5732/MAX5733 improve performance and reduce the board footprint.
Automatic Test Equipment (ATE) Applications
The MAX5734 includes many features suited for ATE applications. The device is the most compact level-setting solution available for high-density pin electronics boards. The MAX5734 provides a -2.5V to +7.5V output voltage range (required by most ATE applications).
24
The offset DAC simultaneously adjusts the voltage range of all 32 DACs, allowing optimization to the application. The remote-sense feature allows the pin electronic voltages to be referenced to the ground potential at the DUT site. The B grade linearity error of 2.44mV (max) is more than sufficient for most ATE applications. The A grade device cuts this error to 1.22mV (max) for higher accuracy. The pipelined register architecture allows all 32 DACs to be updated simultaneously. This is valuable during test setups, as all values in the tester can be set and then updated in unison with a single command. This feature can be accessed through the serial port or the LDAC input. The low output noise of the MAX5734 allows direct connection to the pin electronics, eliminating the cost and PC board area of external filtering. Modern pin electronics integrated circuits (PEICs) are typically fabricated on high-speed processes with low
______________________________________________________________________________________
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface
breakdown voltages. Some devices require external protection on their reference inputs to satisfy absolute maximum ratings. The MAX5734 features outputs that are almost rail-to-rail. This allows the AVCC and VSS supplies to be set to voltages within the absolute maximum ratings of the PEIC. This guarantees that the PEIC is protected in all situations. Additional protection is provided by the MAX5734 glitch-free power-up into the clear state with all DAC outputs set to approximately 0V. Either the serial port or the CLR input can assert the clear function. digital feedthrough and crosstalk. Bypass all power supplies with an additional 0.1F and 1F on each pin, as close to the device as possible. Refer to the MAX5732- MAX5735 evaluation kit for a suggested layout. The MAX5732-MAX5735 have four separate power supplies. AV DD powers the internal analog circuitry (except for the output buffers) and DVDD powers the digital section of the device. AVCC and VSS power the output buffers. The MAX5732-MAX5735 feature an exposed paddle on the backside of the package for improved power dissipation. The exposed paddle is electrically connected to VSS, and should be soldered to a large copper plane that shares the same potential. For more information on the exposed paddle QFN package, refer to the following website: http://pdfserv.maxim-ic.com/arpdf/AppNotes/ 4hfan081.pdf
MAX5732-MAX5735
Power Supplies, Bypassing, Decoupling, and Layout
Grounding and power-supply decoupling strongly influence device performance. Digital signals can couple through the reference input, power supplies, and ground connection. Proper grounding and layout can reduce
Pin Configuration
REFGND OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20
Selector Guide
PART INL (MAX LSB) 8 16 64 8 16 64 8 16 64 8 16 64 8 16 64 8 16 64 8 16 64 8 16 64 OUTPUT VOLTAGE RANGE (V) 0 to +5 0 to +5 0 to +5 0 to +5 0 to +5 0 to +5 0 to +10 0 to +10 0 to +10 0 to +10 0 to +10 0 to +10 -2.5 to +7.5 -2.5 to +7.5 -2.5 to +7.5 -2.5 to +7.5 -2.5 to +7.5 -2.5 to +7.5 -5 to +5 -5 to +5 -5 to +5 -5 to +5 -5 to +5 -5 to +5
TOP VIEW
AVDD
AVCC
MAX5732ACTN MAX5732BCTN
42 AVCC 41 OUT21 40 OUT22 39 VSS 38 AGND 37 OUT23 36 OUT24
56
55 54 53 52
51 50 49 48 47 46 45 44 43
AVCC OUT9 OUT8 OUT7 N.C. OUT6 OUT5 OUT4 AGND
1 2 3 4 5 6 7 8 9
MAX5732CCTN MAX5732AETN MAX5732BETN MAX5732CETN MAX5733ACTN MAX5733BCTN MAX5733CCTN MAX5733AETN MAX5733BETN MAX5733CETN MAX5734ACTN MAX5734BCTN MAX5734CCTN MAX5734AETN MAX5734BETN MAX5734CETN MAX5735ACTN
OUT3 10 VSS 11 OUT2 12 OUT1 13 OUT0 14
MAX5732 MAX5733 MAX5734 MAX5735
35 OUT25 34 OUT26 33 OUT27 32 OUT28 31 OUT29
EXPOSED PADDLE
30 OUT30 29 OUT31
15 16 17 18 19 20 21 22 23 24 25 26 27 28
CS
DOUT
DIN
DGND
LDAC
CLR
GS
REFGND
DVDD
REF
AVDD
DSP
8mm x 8mm THIN QFN-EP
SCLK
Chip Information
TRANSISTOR COUNT: 152,000 PROCESS: BiCMOS
VSS
MAX5735BCTN MAX5735CCTN MAX5735AETN MAX5735BETN MAX5735CETN
______________________________________________________________________________________
25
32-Channel, 16-Bit, Voltage-Output DACs with Serial Interface MAX5732-MAX5735
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
56L THIN QFN.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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